1. Technical Field of the Invention
The present invention generally relates to the field of voltage level translator circuits. In particular it relates to an improved low to high-level voltage translator where the difference between core and I/O supply voltage is very large.
2. Description of Related Art
Advancements in semiconductor fabrication and manufacturing techniques have led to reduction in operating voltage levels. One reason to use lower operating voltage levels is to reduce the power consumption of a semiconductor chip.
Considering the case where the chip is interfaced with bus standards based on higher voltage levels, only the main bulk (or core) of the chip is operated at the lower voltage level while the I/O interface of the chip is operated at a higher voltage level(s). In order to implement such a scheme it is required to translate high voltage I/O signals to low voltage core signals and low voltage core signals to high voltage I/O signals.
One main problem experienced while translating low voltage core signals to high voltage I/O signals relates to direct current paths causing power dissipation. If a low voltage signal is used to drive a device operating at higher voltage, it can cause the device to draw D.C. power since it is neither fully off nor fully on. Thus, circuitry is required for translating voltage signals which can minimize D.C. current problems and thus minimize power dissipation.
FIG. 1 shows a prior art translating circuitry that is an embodiment of U.S. Pat. No. 5,422,523, the disclosure of which is hereby incorporated by reference.
This translator circuitry gives good results when the voltage difference is small, but starts malfunctioning and even fails completely when the difference between the higher and lower supply voltages is large.
FIG. 2 shows the simulation results of the prior art circuitry of FIG. 1 for a higher supply voltage VCC equal to 3.3 V and a lower supply voltage equal to 1.2 V. The output OUT of the translating circuitry is shown for five different operating conditions (as mentioned in FIG. 2 itself). It can be seen that for Condition 1, Condition 2 and Condition 3 the output is acceptable, but for Condition 4 the output becomes distorted and for Condition 5 there is no output (constant low).
The reason for the failure of the circuit is the cross-coupled gates using regenerative feedbacks. In this circuit, switching is initialized by the input signal IN and finally controlled and concluded by regenerative feedback. Switching initialization by the input IN has to ensure that some threshold voltage is reached at the nodes OUT and X before switching is handed over to regenerative feedback. If the initialization process is weak, then the translator circuit will switch late or will not switch at all, and the output OUT will become either distorted or stuck on one state (high or low).
For example, when input IN is at low state, N12 is off, N11 is on, node OUT is at logic low and P12 is on, node X is at logic high and P11 is off. It is to be noted the NMOS transistors N11 and N12 are driven by the lower supply voltage and PMOS transistors P11 and P12 are driven by the higher supply voltage. Now, when input IN switches from low to high, N12 will switch on and will try to pull-down the node X. But in order to pull-down this node N12 has to fight with perfectly turned on PMOS P12. In turn, PMOS P12 will not switch off unless node X goes low effectively. In this case, if N12 is not strong enough to pull-down the node X effectively, the output node OUT will not be pulled-up but will get stuck on logic low.
The same thing may happen in the case of a high to low transition, where N11 has to fight with P11 to pull-down the node OUT. If N11 is not strong enough, output node OUT will not be pulled-down but will get stuck on logic high.
This condition is very likely to occur in the case where the difference between the higher and lower supply voltages is large, as is the case of the example shown in FIG. 2. Referring to the example where a lower supply voltage is 1.2 V and a higher supply voltage is 3.3 V, NMOSs N11, N12 will be switched on with Vgs equal to 1.2 V while PMOS transistors P11, P12 are on with Vgs equal to −3.3 V. The magnitude of the NMOS transistors ‘on’ voltage is very small compared to that of the PMOS transistors; this makes them very weak. Therefore the sizes of the NMOS transistors have to be kept relatively very large to ensure proper functioning. But despite the large size of NMOS transistors, the circuitry still remains very uncertain with variation in operating conditions. When sized nicely to give good results in one operating condition, the circuit gives distorted signals or even no signal in other operating conditions. This can seen from FIG. 2, wherein the circuitry gives good results in Condition 2, gives a distorted signal for Condition 4 and no signal in Condition 5.
The situation becomes even worse when there are bounces on the ground plane. The FIG. 1 translator circuitry is most likely to be used in I/O circuitry, which are inherently noisy. So ground bounce will be a very common event in this circuitry. If ground bounce occurs at the time of input transitions, the effective Vgs of NMOSs will be reduced, thus weakening the transistors further and causing signal distortion.
The situation of having a large difference between higher and lower supply voltages frequently arrives in the case of FPGAs (Field Programmable Gate Arrays) as they are often used for various applications and are therefore interfaced with various devices operating at varied bus standards. Due to the vast and diverse field of applications of FPGAs it becomes desirable to have their I/O interface circuits capable of being programmed to operate at various voltage levels.
In reference to the problems discussed above, there exists a need for a voltage translator circuit that does not have any D.C. current paths so as to minimize power dissipation.